Dividers are used for dividing a frequency of a signal. For example, an output of an oscillator may be divided by a divider into a slower frequency periodic signal relative to the output frequency of the oscillator. Many high performance computing and/or communication systems use on-die system clock frequency with fine resolution, for example, in the order of 10 to 100 Hz. Generally, system clock is generated by a Phase Locked Loop (PLL). The reference input clock for the PLL is generally provided by a fixed frequency crystal oscillator. Since the input frequency of the reference clock is fixed, one way to generate finer system clock frequency is to select a lower reference clock frequency and use an integer divider with as large as possible division ratios to divide the output clock frequency of the PLL to generate a feedback clock signal with same frequency as the reference clock frequency.
However, this method of using integer divider with a large division ratios and lower reference clock frequency limits the design space. For example, generating finer frequency steps in the PLL output clock becomes a challenge. The method and apparatus of using integer divider with large division ratios also causes the system clock's resolution to be limited by the lowest possible reference clock frequency.
When the frequency of the oscillator of the PLL is high, for instance, PLL used for high-speed input-output (I/O) circuits that may be used for inter-chip links, it is non-trivial to design a single-mode divider, let alone dual-modulus dividers.